Summary

Multi-GPU communication has become a major AI performance bottleneck, but a small set of transfer, scheduling, buffering, and synchronization principles can produce substantially better kernels. Current frontier models improve existing implementations only on a limited subset of familiar patterns and still struggle with the underlying systems trade-offs.

Multi-GPU communication has become a major AI performance bottleneck, but a small set of transfe…Read more

Key ideas

Communication Is Becoming the Dominant Bottleneck

Recent progress has reduced the cost of computation and local memory access through techniques such as FlashAttention, sparse attention, Mamba, specialized DSLs, and megakernels. Meanwhile, distributed training and inference increasingly span multiple GPUs and hardware tiers. Communication can therefore consume most of the runtime and suppress model FLOP utilization at scale. The performance frontier is moving from isolated kernel optimization toward communication-aware execution.

Why it matters: Future AI efficiency gains increasingly depend on improving data movement and coordination across devices, not merely accelerating arithmetic on each GPU.

Supporting evidence

So on many production um distributed training and inference workloads, communication is increasingly consuming the majority of the runtime and yields low model flop utilization at scale.

Recent progress has reduced the cost of computation and local memory access through techniques s…Show more

Why it matters: Future AI efficiency gains increasingly depend on improving data movement and coordination across devices, not merely accelerating arithmetic on each GPU.

Supporting evidence

So on many production um distributed training and inference workloads, communication is increasingly consuming the majority of the runtime and yields low model flop utilization at scale.

Networking Improvements Lag Compute Growth

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Overview

As single-GPU kernels and memory-efficient model architectures improve, the performance bottleneck in large AI workloads is shifting toward communication between GPUs. The speaker frames multi-GPU kernel development as a joint optimization problem: developers must maximize hardware utilization while keeping implementations manageable across rapidly changing and vendor-specific networking stacks. The tutorial first grounds this problem in GPU memory hierarchies and interconnects, then contrasts host-initiated copy engines with device-initiated Tensor Memory Accelerator and register-level transfers. It also explains how communication can overlap with computation either within a streaming multiprocessor or across specialized multiprocessors, depending on data alignment and resource pressure. Together AI encapsulates these choices in Parallel Kittens, a compact set of primitives and templates reportedly capable of extending single-GPU kernels with roughly a dozen lines of multi-GPU code. The accompanying Parallel Kernel Bench evaluates whether frontier models can apply the same principles across 87 production-motivated tasks. Results show limited success: the best zero-shot model solves 28 tasks, while additional sampling and an agentic shell environment improve correctness but eventually plateau. The central conclusion is that compilation and syntax repair are increasingly tractable, but reasoning about collective ordering, partitioning, transfer mechanisms, and scheduling remains the decisive weakness.

Sections

Higher-Level Implications

Synthesis of the architectural and evaluation results.

As local GPU execution becomes more efficient, optimization effort must move outward through the system hierarchy: first from arithmetic to on-device memory, and now from on-device memory to inter-device communication.
The networking ecosystem's hardware diversity makes fixed abstractions fragile. A framework tuned to one topology or GPU generation may fail to preserve performance as interconnects, scale-up domains, and in-network capabilities evolve.
The benchmark results imply that successful kernel generation is currently strongest where public examples provide recognizable templates. Performance falls when models must compose unfamiliar scheduling and communication decisions from first principles.
A useful future kernel agent will likely need more than longer execution time: it must connect correctness feedback with topology-aware performance models and explicit exploration of transfer and scheduling alternatives.

Technical Details

Concrete hardware, framework, benchmark, and measurement details presented in the tutorial.

An H100's register memory is described as providing roughly 130 TB/s, illustrating that the fastest storage is also the smallest and closest to the compute units.
The discussed NVIDIA communication hierarchy includes PCIe for CPU-GPU communication, InfiniBand or TCP for multi-node communication, NVLink for GPU-to-GPU point-to-point links, and NVSwitch as a non-blocking fabric with support for operations such as multicast and reduction.
Device-initiated transfer options include Tensor Memory Accelerator and register-level PTX-style instructions described as LD/ST and multimem-related operations.
Parallel Kittens exposes primitives and templates for communication, buffering, and synchronization and reportedly adds about twelve lines to a single-GPU kernel in typical examples.
Parallel Kernel Bench supplies a PyTorch and torch.distributed reference implementation plus rank and intra-node topology information, then asks the model to generate a performant CUDA implementation using unified virtual addressing.
The benchmark contains 87 tasks spanning compositions of data, sequence, tensor, context, layer, pipeline, and expert parallelism.
The benchmark uses pass@k for correctness within k attempts and fast@k for solutions that are both correct and faster than the PyTorch-plus-NCCL reference.
The reported agent experiment combines the mini-SWE-agent multi-turn harness, Gemini 3 Pro, and access to a local Bash environment.

Key Definitions

Terms needed to understand the multi-GPU kernel design space.

Copy engine: A per-GPU, host-initiated transfer mechanism suited to large messages and capable of moving data without consuming substantial GPU register or processor capacity.
Tensor Memory Accelerator: A device-initiated mechanism for asynchronous transfers that can reach high NVLink utilization with relatively small messages while using few registers and processors.
Intra-SM overlap: A schedule in which warps or threads inside the same streaming multiprocessor specialize in computation and communication concurrently.
Inter-SM overlap: A schedule in which separate streaming multiprocessors specialize in compute, communication, or memory work, particularly when their dataflows or resource requirements do not align.
NVSwitch: An interconnect fabric joining NVLink endpoints and supporting full GPU-to-GPU communication as well as selected in-network operations such as multicast and reductions.
Communication-aware roofline: A performance bound that accounts for communication limits when estimating the attainable throughput of a distributed kernel.
Parallel Kittens: A small collection of programming primitives and templates intended to encode recurring high-performance multi-GPU communication patterns.
Parallel Kernel Bench: An 87-problem evaluation suite that tests whether models can transform distributed PyTorch references into correct, faster multi-GPU CUDA kernels.

In Brief Multi GPU communication has become a major AI performance bottleneck, but a small set o…Expand full summary

Overview

Sections

Higher-Level Implications

Synthesis of the architectural and evaluation results.

As local GPU execution becomes more efficient, optimization effort must move outward through the system hierarchy: first from arithmetic to on-device memory, and now from on-device memory to inter-device communication.
The networking ecosystem's hardware diversity makes fixed abstractions fragile. A framework tuned to one topology or GPU generation may fail to preserve performance as interconnects, scale-up domains, and in-network capabilities evolve.
The benchmark results imply that successful kernel generation is currently strongest where public examples provide recognizable templates. Performance falls when models must compose unfamiliar scheduling and communication decisions from first principles.
A useful future kernel agent will likely need more than longer execution time: it must connect correctness feedback with topology-aware performance models and explicit exploration of transfer and scheduling alternatives.

Technical Details

Concrete hardware, framework, benchmark, and measurement details presented in the tutorial.

An H100's register memory is described as providing roughly 130 TB/s, illustrating that the fastest storage is also the smallest and closest to the compute units.
The discussed NVIDIA communication hierarchy includes PCIe for CPU-GPU communication, InfiniBand or TCP for multi-node communication, NVLink for GPU-to-GPU point-to-point links, and NVSwitch as a non-blocking fabric with support for operations such as multicast and reduction.
Device-initiated transfer options include Tensor Memory Accelerator and register-level PTX-style instructions described as LD/ST and multimem-related operations.
Parallel Kittens exposes primitives and templates for communication, buffering, and synchronization and reportedly adds about twelve lines to a single-GPU kernel in typical examples.
Parallel Kernel Bench supplies a PyTorch and torch.distributed reference implementation plus rank and intra-node topology information, then asks the model to generate a performant CUDA implementation using unified virtual addressing.
The benchmark contains 87 tasks spanning compositions of data, sequence, tensor, context, layer, pipeline, and expert parallelism.
The benchmark uses pass@k for correctness within k attempts and fast@k for solutions that are both correct and faster than the PyTorch-plus-NCCL reference.
The reported agent experiment combines the mini-SWE-agent multi-turn harness, Gemini 3 Pro, and access to a local Bash environment.

Key Definitions

Terms needed to understand the multi-GPU kernel design space.

Copy engine: A per-GPU, host-initiated transfer mechanism suited to large messages and capable of moving data without consuming substantial GPU register or processor capacity.
Tensor Memory Accelerator: A device-initiated mechanism for asynchronous transfers that can reach high NVLink utilization with relatively small messages while using few registers and processors.
Intra-SM overlap: A schedule in which warps or threads inside the same streaming multiprocessor specialize in computation and communication concurrently.
Inter-SM overlap: A schedule in which separate streaming multiprocessors specialize in compute, communication, or memory work, particularly when their dataflows or resource requirements do not align.
NVSwitch: An interconnect fabric joining NVLink endpoints and supporting full GPU-to-GPU communication as well as selected in-network operations such as multicast and reductions.
Communication-aware roofline: A performance bound that accounts for communication limits when estimating the attainable throughput of a distributed kernel.
Parallel Kittens: A small collection of programming primitives and templates intended to encode recurring high-performance multi-GPU communication patterns.
Parallel Kernel Bench: An 87-problem evaluation suite that tests whether models can transform distributed PyTorch references into correct, faster multi-GPU CUDA kernels.

	Copy Engine	Tensor Memory Accelerator	Register-Level Instructions
Initiation and best fit	Host or CPU initiated; best for large messages	Device initiated; suited to fine-grained transfers	Device initiated; suited to direct low-level communication
GPU resource use	Uses few GPU registers and no GPU processors for the transfer	Consumes very few registers and can achieve high utilization with few processors	Uses register-level operations
In-network computation	Not identified as its main advantage	Cannot effectively exploit the described in-network computations	Can exploit capabilities such as NVSwitch reductions

Can LLMs Write Fast Multi-GPU Kernels? - Simran Arora, Together AI

Summary

Key ideas

Communication Is Becoming the Dominant Bottleneck

Networking Improvements Lag Compute Growth

Standard Collective Libraries Favor Simplicity Over Fine-Grained Performance

Multi-GPU Transfer Mechanisms

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Overview

Sections

Higher-Level Implications

Technical Details

Key Definitions

Overview

Sections

Higher-Level Implications

Technical Details

Key Definitions